US Patent 7521307 CMOS structures and methods using self-aligned dual stressed layers

A CMOS structure and methods for fabricating the CMOS structure provide that a first stressed layer located over a first transistor and a second stressed layer located over a second transistor abut but do not overlap. Such an abutment absent overlap provides for enhanced manufacturing flexibility when forming a contact to a silicide layer upon a source/drain region within one of the first transistor and the second transistor.