Patent attributes
An amplifier that amplifies an input signal and provides the amplified signal to a load at a summing junction that has a first impedance value. The amplifier includes a splitter network receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier and a first output match network coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier, a second output match network coupled to the peaking amplifier, and a phase delay element coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.
