Patent attributes
A memory cell array includes a plurality of memory cells enabled to store multi-value data. A bit-line control circuit includes data storage circuits connected to bit-lines and each store one of a plurality of sets of page data included in the multi-value data, the bit-line control circuit controlling bit-line voltages applied to the bit-lines. A word-line control circuit controls a word-line voltage applied to a word-line. A control circuit controls the word-line control circuit and the bit-line control circuit. The control circuit performs a mode in which, to distinguish a fault block, all or specific memory cells in a fault block may be written so that all or specific memory cells in the fault block have a threshold voltage higher than a word-line voltage applied to a selected word-line when reading a first page data of the sets of page data.
