US Patent 7522458 Memory and method of controlling access to memory

A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.