US Patent 7523428 Hierarchical signal integrity analysis using interface logic models
Patent 7523428 was granted and assigned to Synopsys on April, 2009 by the United States Patent and Trademark Office.
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Performing signal integrity (SI) analysis on integrated circuit designs is becoming increasingly important as these designs increase in size and complexity. Dividing a design into blocks can simplify the resulting analysis. Additionally, such blocks can be replaced with timing models, which provide a compact means of exchanging interface timing information for the blocks. To further increase the speed and accuracy of SI analysis, enhanced interface logic models (SI-ILMs) can be used. An SI-ILM can include cells in timing paths that serve as the interface between the block and other parts of the design. The SI-ILM can also include internal nets that have cross-coupling effects on interface nets and nets outside the block. By including these internal nets, SI analysis at the top-level can be both fast and accurate.
US Patent 07523428 Hierarchical signal integrity analysis using interface logic models US Patent 7523428 Hierarchical signal integrity analysis using interface logic models
US Patent 07523428 Hierarchical signal integrity analysis using interface logic models
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