Patent attributes
A logic design system is provided for designing programmable logic device integrated circuits with minimized simultaneous switching noise. The logic design system identifies input-output drivers that are associated with simultaneous switching noise groups by examining a netlist for a circuit design for a programmable logic device. Simultaneous switching noise is minimized by making adjustments to programmable operating parameters for the input-output drivers. The logic design system may make adjustments such as adjustments to programmable drive strengths, programmable slew rates, and programmable on-chip termination resistances. During place and route operations, the logic design system makes placement decisions that help to minimize simultaneous switching noise.
