Patent attributes
A clock receiver for an integrated circuit includes duty-cycle correction capabilities based on monitoring an average value associated with an internally generated clock signal. An active adjustment circuit within the clock receiver provides correction to each leg of the differential clock signal based on two correction signals. The correction signals are derived from a comparison of the average value associated with the internal clock signal with a target voltage. The target voltage is based on a trip-point of an inverter stage in a logic stage that is driven by the internal clock signal. The closed loop control of the correction signals adjusts the average value of the internal clock signal until it is substantially equal to the target voltage. By straddling the internal clock signal about the trip-point of the inverter stage, the duty-cycle associated with the internal clock signal is adjusted to substantially a 50% duty cycle.
