US Patent 7525363 Delay line and delay lock loop

A delay line comprises first and second delay arrays and a multiplexer. The first delay array receives a clock signal and a delay control signal, and delays the clock signal to output a first delay array clock signal according to the delay control signal. The second delay array receives a power control signal, the first delay array clock signal and the delay control signal. The second delay array is turned on or off according to the power control signal. If the second delay array is turned on, the second delay array delays the first delay array clock signal to output a second delay array clock signal according to the delay control signal. The multiplexer receives a selecting control signal, the first and second delay array clock signals, and outputs the first delay array clock signal or the second delay array clock according to the selecting control signal.