Patent attributes
A row decoder circuit is described of the type comprising at least one input stage connected to a first supply voltage reference and to an output stage connected to a second supply voltage reference, the output stage having at least one output terminal connected to a word line of a memory matrix. The row decoder circuit further comprises a biasing device, connected to a third supply voltage reference and comprising at least one generator of a negative voltage connected to a divider, in turn connected to a first biasing terminal of the biasing device. In particular, the first biasing terminal is connected to at least one input stage in correspondence with bulk terminals of MOS transistors comprised in the input stage and it is suitable for supplying it with a first negative voltage.
