Patent attributes
Circuitry is provided in a programmable logic device incorporating clock-data recovery circuitry on I/O channels to allow the use of otherwise unused noise-reduction circuits in the I/O channels, such as decision-feedback equalization (DFE) circuits, to cancel or minimize cross-talk with other channels or other sources of cross-talk. Selectable connections are provided to allow various potential sources of cross-talk to be programmably connected to the DFE circuits instead of unused CDR output taps. When a user finalizes a user logic design, the user can determine the sources of cross-talk and the unused taps relative to a particular channel, and programmably connect the sources to the DFE circuits corresponding to those unused taps. DFE coefficients may then be adjusted to cancel or at least minimize the cross-talk. Programmable time delays can be provided to adjust for clock differentials between the cross-talk source and the particular channel under consideration.
