US Patent 7532250 Clock generation apparatus

A clock generation apparatus is provided with a frequency phase error calculation circuit 120, whereby a clock synchronized with burst lock and a line lock clock can be simultaneously generated by a DTO 121 on the basis of frequency information of a DTO 10 and phase error information from a phase comparator 7 and a digital LPF 8. Therefore, the clock generation apparatus can cope with a system that required plural clocks, and frequency spread is easily carried out by generating spread information by a frequency spread information generation circuit 90, and adding it in the DTO 121. As a result, interference to a video terminal from the clock can be reduced, and performance of a video terminal such as a television receiver can be exploited.