Patent attributes
A memory subsystem. A memory subsystem includes a memory controller coupled to a processor and a plurality of N memory modules. The memory controller is directly coupled to convey information to the Nth memory module through a downstream link, and is directly coupled to receive information from a first memory module through an upstream link. Each of the memory modules may be coupled to a prior memory module via a downstream link. Information conveyed from the memory controller to a particular memory module is conveyed to the Nth memory module through the downstream link and, as necessary, through additional downstream links to the particular memory module. Each of the memory modules may be coupled to receive data from a subsequent memory module via an upstream link. Information conveyed from a memory module to the memory controller is conveyed from the memory module through upstream links to the memory controller.
