Patent attributes
The present invention provides a fabrication method of a display device which aims at the reduction of fabricating man-hours. In a fabrication method of a display device having a thin film transistor in which a gate electrode includes a first gate electrode and a second gate electrode which is overlapped to the first gate electrode and has a size thereof in the channel direction set smaller than the corresponding size of the first gate electrode, the semiconductor layer includes a channel region which is overlapped to the second gate electrode, a first impurity region which is overlapped to the first gate electrode and is formed outside the second gate electrode, a second impurity region which is formed outside the gate electrode, and a third conductive impurity region which is formed outside the gate electrode and the second impurity region, the first impurity region, the second impurity region and the third impurity region are respectively formed of the same conductive type, the impurity concentration of the first impurity region is lower than the impurity concentration of the third impurity region, and the impurity concentration of the second impurity region is lower than the impurity concentration of the first impurity region, impurities are collectively implanted into both of the first and second impurity regions such that the impurities are implanted into the first impurity region by way of the first gate electrode and the impurities are implanted into the second impurity region such that a peak position of the impurity concentration in the depth direction is positioned below the semiconductor layer thus lowering the impurity concentration of the second impurity region than the impurity concentration of the first impurity region.
