US Patent 7535242 Interface test circuit

An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.