Patent attributes
A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
