Patent attributes
A resynchronization circuit possesses a sufficient migration margin even when the speed of a clock signal used for outputting data is increased, so that the data transfer speed can be increased. In the resynchronization circuit, a determination circuit holds a signal which is determined according to the phase difference between a determination signal and a reference clock signal (determination result). In a synchronization circuit block, a received data signal is held in synchronization with a strobe signal. Then, the received data signal is held in synchronization with a clock signal which has the same frequency as that of the reference clock signal and has a phase determined according to the determination result and output from the resynchronization circuit.
