US Patent 7538408 Inhibition of parasitic transistor operation in semiconductor device

A semiconductor device includes a surface layer on the side of a first principal surface of a p-semiconductor substrate, a high side n-isolation-diffused region and a low side n-isolation-diffused region formed apart from each other by a distance that is shorter than the diffusion length of electrons in the p-semiconductor substrate. In a region between the high side n-isolation-diffused region and the low side n-isolation-diffused region, a p-region is formed which has a higher impurity concentration than the p-semiconductor substrate. A first electrode in contact with the p-region and a second electrode in contact with a second principal surface of the p-semiconductor substrate are brought to be at the ground potential. This, at switching of a low side IGBT, makes a charging or discharging current flowing from the high side n-isolation-diffused region flow toward the back surface of the substrate to be taken out from the second electrode.