US Patent 7539078 Circuits to delay a signal from a memory device

Various apparatus and methods include a clock circuit to receive a first clock signal to generate a second clock signal having a frequency different from a frequency of the first clock signal. A clock capturing circuit receives the second clock signal for determining a number of delay elements corresponding to an amount of a period of the second clock signal. A delay calculation circuit calculates an amount of time corresponding to the number of delay elements. And a delay circuit delays an input control signal by the amount of time provided by the delay calculation circuit.