Patent attributes
Correction of glitches output from a delta-sigma modulator is accomplished using an integer boundary crossing detector and a FIR filter. The detector monitors a portion of an input to the modulator. The detector recognizes a transition from an all 1's bit pattern to an all 0's bit pattern or vice versa as representative of potential for a glitch to be present on the output of the modulator. The detector responsively generates condition detection output. Receipt of such condition detection output triggers the generation of a correction signal by the filter. The correction signal is, at least substantially similar, in magnitude but opposite in sign from to the expected glitch at the output of the modulator. The correction signal is added to the output of the modulator to substantially eliminate the glitch.
