US Patent 7542343 Planar NAND flash memory

Time-domain sensing scheme is introduced for reading NAND flash memory cell, wherein cell current is converted to voltage by discharging bit line, which voltage is amplified by a segment read circuit, then the voltage difference is converted to time difference by a block read circuit. In this manner, a reference signal is generated by reference cells storing low threshold data, which signal is delayed by a delay circuit for generating a locking signal. Thus the locking signal effectively rejects latching high threshold data in latch circuits because high threshold data is arrived later. Furthermore, by adopting multi-divided bit line architecture, discharging time of bit line is reduced. In addition, layout of the segment read circuit is repeatedly placed next to cell arrays in order to fabricate in the conventional planar CMOS process environment.