US Patent 7545173 Level shift delay equalization circuit and methodology
Patent 7545173 was granted and assigned to Linear Technology on June, 2009 by the United States Patent and Trademark Office.
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Transition delays in a level shift circuit are equalized by generating a first signal related to the state of the input signal, a second signal inversely related to the state of the input signal, and a third signal that is reciprocal to the second signal. Upon transition of the input signal from a high state to a low state, the third signal is selected for controlling the output until the first signal attains a high state. The first signal is selected for controlling the output when it has reached a high state after the input signal transition. The first signal remains selected upon transition of the input signal from a high state to a low state. Thus, output delays are equalized and reduced to the shortest delay.
US Patent 07545173 Level shift delay equalization circuit and methodology US Patent 7545173 Level shift delay equalization circuit and methodology
US Patent 07545173 Level shift delay equalization circuit and methodology
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