Patent attributes
A PLL circuit according to the present invention includes: a voltage controlled oscillator 10; a frequency divider 30 that divides an oscillation signal of the voltage controlled oscillator 10 and outputs a divided oscillation signal; a first phase comparator 40 that outputs a phase difference between the divided oscillation signal of the frequency divider 30 and a reference signal; a charge pump 60 that converts the output signal of the first phase comparator 40 into a signal for controlling the voltage controlled oscillator 10; a filter that allows a DC component of the output signal of the charge pump 60 to pass therethrough and outputs a voltage to the voltage controlled oscillator 10; a second phase comparator 90 that averages the phase difference between the divided oscillation signal of the frequency divider 30 and the reference signal with respect to time; and a current control circuit 100 that controls an operating current of the frequency divider 30 based on the phase difference averaged with respect to time by the second phase comparator 90. With this configuration, it is possible to provide a PLL circuit that achieves low power consumption and covers a wide range of oscillation frequencies.
