Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Date of Patent
June 16, 2009
Patent Application Number
11501129
Date Filed
August 7, 2006
Patent Primary Examiner
Patent abstract
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
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