US Patent 7551240 Electrostatic discharge (ESD) protection circuit integrated with cell test function

A flat display including a display panel is disclosed. The display panel includes several signal lines and ESD protection circuits whose negative ESD protection circuits have cell test function. When a driving IC bonds to the display panel, the system operates in a normal dynamic display mode, and the negative ESD protection circuits are coupled to a low-level voltage such that thin film transistors of the negative ESD protection circuit are switched off in the normal display mode. Therefore, the power consumption of the panel module can be reduced and using time of the products can be improved.