Patent attributes
A chip embedded package structure and a fabrication method thereof are proposed. An adhesive layer is formed on a bottom surface of a carrier board having at least one cavity to seal one end of the cavity. At least one semiconductor chip is mounted via its non-active surface on the adhesive layer and received in the cavity. A protection layer is formed on an active surface of the semiconductor chip. A conductive layer is formed on a top surface of the carrier board, the protection layer and the cavity. A patterned resist layer is applied on the conductive layer and is formed with an electroplating opening at a position corresponding to a gap between the cavity and the semiconductor chip. An electroplating process is performed to form a metal layer in the electroplating opening, such that the semiconductor chip can be effectively fixed in the cavity by the metal layer.
