US Patent 7555083 Synchronizing circuit for stably generating an output signal

The present invention relates to a synchronizing circuit for stably generating an output signal irrespective of the frequency difference of clocks. According to the present invention, the synchronizing circuit receives an input signal synchronized with a first clock and then stores a state of the input signal so that the input signal is synchronized with a transition of a second clock. then, the synchronizing circuit generates an output signal synchronized with the transition of the second clock. In addition, an input signal synchronized with the first clock becomes synchronized with the second clock having a lower frequency than the first clock.