Patent attributes
A wiring layer having an antireflection film of TiN or the like is formed on an insulating film covering a principal surface of a semiconductor substrate, and thereafter an interlayer insulating film including first to third insulating films is formed covering the wiring layer. The first and third insulating films are silicon oxide films formed by PE CVD or the like, and the second insulating film is a coated insulating film of inorganic or organic SOG. A contact hole is formed through the interlayer insulating film in a region corresponding to a partial surface area of the wiring layer, by dry etching using a resist layer as a mask. The coated insulating film, which is likely to be subjected to side etching, is etched under a highly depositive condition not containing N2, and thereafter the lower insulating film is etched under a lowly depositive condition containing N2.
