Patent attributes
A power semiconductor arrangement has an electrically insulating and thermally conductive substrate, which is provided with structured metallization on at least one side, a cooling device which is in thermal contact with the other side of the substrate, at least one semiconductor component which is arranged on the substrate and is electrically connected to the structured metallization, an entirely or partially electrically insulating film which is arranged at least on that side of the substrate at which the at least one semiconductor component is placed, and which is laminated without any cavities onto the substrate including or excluding the at least one semiconductor component, and a contact-pressure device which exerts a force on the substrate locally and via the at least one semiconductor component such that the substrate is pressed against the cooling device.
