Patent attributes
A semiconductor device of the invention comprises a logic circuit to which a power supply voltage, a sub-power supply voltage lower than the power supply voltage, a ground voltage and a sub-ground voltage higher than the ground voltage are supplied; a main power supply line supplying the power supply voltage; and a main ground line supplying the ground voltage. A unit circuit constituting the logic circuit includes first to third PMOS transistors and first to third PMOS transistors. The third PMOS transistor is connected between sources of the first and second PMOS transistors, the main power supply line is connected to its one node, and the sub-power supply voltage is generated at its other node. The third NMOS transistor is connected between sources of the first and second NMOS transistors, the main ground line is connected to its one node, and the sub-ground voltage is generated at its other node.
