Patent attributes
A NAND flash memory device includes: a memory cell array that includes a plurality of NAND memory cell units each including a connection element having a plurality of electrically-rewritable memory cells; a plurality of word lines that are connected to the plurality of memory cells; a plurality of bit lines that are connected to the plurality of memory cells; and a read-write control section that applies a voltage selectively to the plurality of word lines and the plurality of bit lines, wherein each of the plurality of NAND memory cell units includes a first select gate transistor and a second select gate transistor; and wherein the read-write control section sets an voltage level applied to word lines, so that the voltage level becomes lower than a predetermined voltage level applied to other word lines connected to control gate electrodes of memory cells.
