Patent attributes
A method for synchronizing an output signal of a device phase aligned with an input clock includes the steps of providing an oscillator signal having a period Πn of 1/(f1*2n), wherein f1 is the clock frequency, and wherein the oscillator signal is phase aligned with the input clock signal, so a multiple of the clock frequency is produced. A number of delayed signals are generated, each having the same period as the input clock signal, but delayed by multiples of one-half the oscillator period from the input clock. The phase difference between the unadjusted output signal each delayed signal is determined, and the smallest value of the phase difference calculated. This smallest phase difference value is then added to the clock signal, resulting in a delayed clock, which is then used to generated the delayed output signal, which will be in close synchronization with the input clock.
