US Patent 7565466 Memory including an output pointer circuit

A memory including an input register, an input pointer circuit, and an output pointer circuit. The input register is configured to receive and latch-in valid and invalid data via an input pointer and to output the valid data via an output pointer. The input pointer circuit is configured to provide the input pointer based on a continuously running write data strobe clock signal. The output pointer circuit is configured to provide the output pointer based on an external clock signal and to update the output pointer to point to the valid data in the input register based on a write signal.