Patent attributes
The present invention provides a memory device of a type that outputs a ready signal to the outside, and that is capable of achieving an enhanced data transfer rate and a uniform latency time. A memory device according to the present invention includes a ready signal sending portion, and the ready signal sending portion monitors a memory portion to detect the memory portion becoming ready for reading or writing of specified data. The ready signal sending portion generates a first ready signal that changes from a busy state to a ready state after the detection and an enabling signal that changes from a disable state to an enable state on the basis of a preset ready generating timing value. When the first ready signal is in the ready state and the enabling signal is in the enable state, the ready signal sending portion sends to the outside a second ready signal that is in a ready state.
