US Patent 7570507 Quasi-differential read operation

A memory device includes an array portion of resistive memory cells comprising a plurality of bit line pairs. The device further includes a read circuit operably associated with a first charged line, wherein the read circuit comprises a precharge circuit configured to charge a first line at a first rate, and to charge a second line at a second rate, the first and second charge rates based on a state of a memory cell coupled between the respective lines. The read circuit may further include a ground circuit configured to pull the respective lines to a ground potential, and a sense circuit coupled to the line pair configured to sense a differential voltage between the line pair in response to the state of the memory cell.