Patent attributes
A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.
