Patent 7571408 was granted and assigned to Cadence Design Systems on August, 2009 by the United States Patent and Trademark Office.
An IC device and layout having one or more layers having route segments and at least some shield segments that are diagonal in orientation. Shield termination segments enclosing a route segment may be diagonal in orientation. Some embodiments describe a method for providing diagonal shielding for a routed net of an IC layout. A route “bloating” method is used where shield position lines (used to position the shielding) are generated by expanding out the dimensions of routes using a bloating shape. The bloating shape that may be dependent on the preferred wiring direction of the layer on which the shielding is provided. After bloating a route, a resulting bloating geometry is identified comprising the area overlapped during the expanding out of the route. The perimeter of the bloating geometry is identified comprising the shield position lines.