Patent attributes
There is provided a test apparatus that tests a device under test including a plurality of data terminals and a clock output terminal, the test apparatus including a plurality of first variable delay circuits that delays a reference clock, a plurality of timing clock generating sections that outputs a timing clock having a phase obtained by shifting a phase of the delayed reference clock by a designated phase shift amount, a timing comparator that acquires a data signal in accordance with the timing clock, a plurality of second variable delay circuits that delays the timing clock, a plurality of phase comparators that outputs a phase shift amount according to a phase difference between a clock signal and the timing clock, a first adjusting section that adjusts a delay amount of the first variable delay circuit so that the timing comparator acquires a data signal based on the timing clock, and a second adjusting section that adjusts a delay amount of the second variable delay circuit so that the timing comparator acquires the data signal based on the clock signal.
