US Patent 7576412 Wafer with improved sawing loops

In a wafer (1) with chips (2) and elongate separating zones (4) between the chips (2), each chip (2) comprises at least one sawing loop (6), which sawing loop (6) comprises two protecting strips (17, 18) projecting from a planar protecting layer (16) of the chip (2), wherein said protecting strips (17, 18) are widened by means of wider strip portions (26, 27, 28, 29) where they emerge from the planar protecting layer (16), and wherein the protecting strips (17, 18) and the planar protecting layer (16) are provided with weak spots (31, 32, 34) serving as envisaged breakage points.