US Patent 7576580 Energy efficient clock deskew systems and methods

Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based distributed clock deskew technique. The disclosed technique has broad commercial/industrial applicability, e.g., in VLSI/ULSI chips, such as microprocessors, digital signal processing systems (DSPs), integrated circuits, application-specific integrated circuits (ASICs), micro-controllers, embedded systems, memory chips and the like.