US Patent 7577049 Speculative sense enable tuning apparatus and associated methods

A computer memory includes a sense enable control module for generating a sense enable signal for a memory core. The sense enable control module includes an active side for transmitting the sense enable signal for the memory core, and a calibration side for determining when the sense enable signal is to be transmitted by the active side. Both the active side and the calibration side are defined to receive a timing signal. The active side is defined to transmit a delayed version of the timing signal as the sense enable signal for the memory core. The calibration side is defined to adjust the delay amount associated with the delayed version of the timing signal to be transmitted by the active side based on a determined sufficiency of the delay amount.