US Patent 7581065 Low locality-of-reference support in a multi-level cache hierachy
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Patent Inventor Names
Dennis M. O'Connor0
Michael W. Morrow0
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Patent abstract
A processor includes a multi-level cache hierarchy where locality information property such as a Low Locality of Reference (LLR) property is associated with a cache line. The LLR cache line retains the locality information and may move back and forth within the cache hierarchy until evicted from the outer-most level of the cache hierarchy.
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US Patent 07581065 Low locality-of-reference support in a multi-level cache hierachy US Patent 7581065 Low locality-of-reference support in a multi-level cache hierachy
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Patent Number
075810650
Patent Number
75810650
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Patent Jurisdiction
Patent Number
075810650
Date of Patent
August 25, 2009
0Patent Application Number
111017850
Date Filed
April 7, 2005
0Official Website
Patent Primary Examiner
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US Patent 07581065 Low locality-of-reference support in a multi-level cache hierachy
Infobox
Is a
Patent jurisdiction
Patent number
07581065
Date of patent
August 25, 2009
Patent application number
11101785
Date Filed
April 7, 2005
Patent primary examiner
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