Patent attributes
A semiconductor device including a memory cell having a memory transistor and select gate transistor and a peripheral transistor is disclosed. The memory transistor has a stacked gate structure formed by sequentially stacking a gate insulating film, first gate electrode, inter-poly insulating film, and second gate electrode on a semiconductor substrate. The select gate transistor has a stacked gate structure identical to the memory transistor, and selects the memory transistor. The peripheral transistor forms a peripheral circuit of the memory cell, and has a gate electrode having a single-layer structure. A through hole reaching the first gate electrode is formed in the second gate electrode and inter-poly insulating film positioned on an element isolation film of the select gate transistor. A contact plug buried in this through hole electrically connects the second gate electrode and first gate electrode.
