Patent attributes
A nonvolatile semiconductor memory device includes a plurality of 3-dimensional cell arrays to reduce the chip size. The nonvolatile semiconductor memory device includes a unit block cell array including a plurality of vertically multi-layered cell arrays each including a plurality of unit cells arranged in row and column directions, a column address decoder configured to decode a column address to activate a bit line of the selected cell array from the plurality of cell arrays, a sense amplifier unit configured to sense and amplify data of the bit line of the plurality of cell arrays and shared by the unit block cell array, and a vertical address decoding unit configured to decode a vertical address to select one of the plurality of cell arrays and to connect an output signal from the sense amplifier to the bit line of the selected cell array.
