US Patent 7584330 Multi-processor data coherency

A method for maintaining coherent data in a multiprocessor system having a plurality of processors coupled to main memory, where each processor has an internal cache which is externally unreadable outside the processor. The method includes requesting data associated with a memory location in main memory and determining if an external cache coupled to an application specific integrated circuit associated with a second processor contains a reference to the requested data. A snoop cycle is performed on the second processor if the external cache has a reference to the requested data, whereupon a determination is made as to whether the requested data has been modified.