Patent attributes
A digital frequency/phase recovery circuit includes a comparator with hysteresis, a counter, a frequency determiner, a multi-phase clock generator, a transition detector, a phase adjuster, and a multiplexer. The comparator with hysteresis receives the input signal and generates a comparison signal. The counter receives the comparison signal, calculates the pulse number of the comparison signal in one period, and outputs a pulse value. The frequency determiner receives the pulse value, calculates the frequency of the input signal, and generates a frequency value. The multi-phase clock generator receives the frequency value and generates multi-phase reference clocks according to the frequency value. The transition detector receives the comparison signal and generates a transition signal. The phase adjuster receives the transition signal and the sampling clock and generates a phase selection signal, and the multiplexer receives the multi-phase reference clocks and selects one reference clock as the sampling clock according to the phase selection signal.
