US Patent 7587545 Shared memory device

A shared memory device able to simplify interconnects up to memories, able to prevent a reduction of performance due to an increase of area and longer interconnects, and able to speed up memory access, wherein an input/output port of a processing module, memory interfaces, and memory banks are connected by connection interconnects arranged in a matrix in a first direction and a second direction above an arrangement region of a plurality of memory macros.