Patent attributes
A delay calculation apparatus is provided for delay calculation of a structured ASIC in which a clock circuit is integrated within a master slice. The delay calculation apparatus is composed of a storage unit storing a clock circuit delay library containing clock circuit delay data obtained by delay calculation of a clock circuit, and a delay calculation section performing delay calculation of a structured ASIC incorporating the clock circuit to thereby generate delay calculation result data of the structured ASIC. The delay calculation section is designed to obtain at least a portion of the clock circuit delay data from the clock circuit delay library, and to merge the obtained portion of the clock circuit delay data into the delay calculation result data.
