US Patent 7589550 Semiconductor device test system having reduced current leakage

A test circuit tests a device under test (DUT) uses a first switching device and a second switching device. The device under test (DUT) has a terminal for receiving a test signal. The first switching device has an output terminal for use in coupling the test signal to the terminal of the DUT when the DUT is being tested. The first switching device is high impedance when the DUT is not being tested. The second switching device is high impedance when the DUT is being tested and couples a bias control signal to the output terminal of the first switching device when the DUT is not being tested. The bias control signal substantially tracks the test signal. Leakage from the first switching device when other DUTs are being tested is greatly reduced because the bias control signal results in little or no bias across the first switching device.