US Patent 7590013 Semiconductor memory devices having variable additive latency

A semiconductor memory device includes an additive latency setting unit configured to receive a mode setting code from an external unit in response to the mode setting signal during a mode setting operation, set an additive latency value in response to the mode setting code, and receive the mode setting code in response to the additive latency setting signal during a normal operation, and an additive latency changing unit configured to change the additive latency value in response to the mode setting code during the normal operation.