Patent attributes
A method for driving a plasma display panel (PDP) and for safely erasing wall charges in an erase period. The PDP includes a middle (M) electrode formed between an X electrode and a Y electrode. A sustain discharge pulse voltage is periodically applied to the X electrode and the Y electrode in a pulse train fashion. In addition, a reset waveform, a scan pulse voltage, and a sustain discharge voltage are applied to the middle electrode. Moreover, to prevent a strong discharge, an erase waveform is applied to the M electrode in the erase period while the X and Y electrodes are biased with the same voltage level. Alternatively, to prevent a strong discharge, an erase waveform (a gradually rising waveform) is applied to the X electrode in the erase period while the M and Y electrodes are biased with the same voltage level (a ground voltage).
